vs-p100 series www.vishay.com vishay semiconductors revision: 27-mar-14 1 document number: 93754 for technical questions within your region: diodesamericas@vishay.com , diodesasia@vishay.com , diodeseurope@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 power modules, passivated assembled circuit elements, 25 a features ? glass passivated junction s for greater reliability ? electrically isolated base plate ? available up to 1200 v rrm /v drm ? high dynamic characteristics ? wide choice of circuit configurations ? simplified mechanical design and assembly ? ul e78996 approved ? material categorization: for definitions of compliance please see www.vishay.com/doc?99912 description the vs-p100 series of integrated power circuits consists of power thyristors and power diodes configured in a single package. with its isolating base plate, mechanical designs are greatly simplified giving advantages of cost reduction and reduced size. applications include power supplies, control circuits and battery chargers. electrical specifications product summary i o 25 a type modules - thyristor, standard package pace-pak (d-19) circuit single phase, hybrid br idge common cathode, single phase, hybrid br idge doubler connection, single phase, all scr bridge pace-pak (d-19) major ratings and characteristics symbol characteristics values units i o 85 c 25 a i tsm 50 hz 357 a 60 hz 375 i 2 t 50 hz 637 a 2 s 60 hz 580 i 2 ? t 6365 a 2 ? s v drm , v rrm 400 to 1200 v v isol 2500 v t j range -40 to 125 c t stg -40 to 125 c voltage ratings type number v rrm /v drm , maximum repetitive peak reverse and peak off-state voltage v v rsm , maximum non-repetitive peak reverse voltage v i rrm maximum at t j maximum ma VS-P101, vs-p121, vs-p131 400 500 10 vs-p102, vs-p122, vs-p132 600 700 vs-p103, vs-p123, vs-p133 800 900 vs-p103, vs-p124, vs-p134 1000 1100 vs-p105, vs-p125, vs-p135 1200 1300
vs-p100 series www.vishay.com vishay semiconductors revision: 27-mar-14 2 document number: 93754 for technical questions within your region: diodesamericas@vishay.com , diodesasia@vishay.com , diodeseurope@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 on-state conduction parameter symbol test conditions values units maximum dc output current at case temperature i o full bridge 25 a 85 c maximum peak, one-cycle non-repetitive on-state or forward current i tsm , i fsm t = 10 ms no voltage reapplied sinusoidal half wave, ? initial t j = t j maximum 357 a t = 8.3 ms 375 t = 10 ms 100 % v rrm reapplied 300 t = 8.3 ms 315 maximum i 2 t for fusing i 2 t t = 10 ms no voltage reapplied 637 a 2 s t = 8.3 ms 580 t = 10 ms 100 % v rrm reapplied 450 t = 8.3 ms 410 maximum i 2 ? t for fusing i 2 ? t t = 0.1 ms to 10 ms, no voltage reapplied ? i 2 t for time tx = i 2 ? t ? tx 6365 a 2 ? s maximum value of threshold voltage v t(to) t j = 125 c 0.82 v maximum level value of on-state slope resistance r t1 t j = 125 c, average power = v t(to) x i t(av) + r t + (i t(rms) ) 2 12 m ? maximum on-state voltage drop v tm i tm = ? x i t(av) t j = 25 c 1.35 v maximum forward voltage drop v fm i fm = ? x i f(av) t j = 25 c 1.35 v maximum non-repe titive rate of rise of turned-on current di/dt t j = 125 c from 0.67 v drm ? i tm = ? x i t(av) , i g = 500 ma, t r < 0.5 s, t p > 6 s 200 a/s maximum holding current i h t j = 25 c anode supply = 6 v, resistive load, gate open 130 ma maximum latching current i l t j = 25 c anode supply = 6 v, resistive load 250 blocking parameter symbol test conditions values units maximum critical rate of rise of off-state voltage dv/dt t j = 125 c, exponential to 0.67 v drm gate open 200 v/s maximum peak reverse and off-state leakage current at v rrm , v drm i rrm , i drm t j = 125 c, gate open circuit 10 ma maximum peak reverse leakage current i rrm t j = 25 c 100 a rms isolation voltage v isol 50 hz, circuit to base, all terminals shorted, ? t j = 25 c, t = 1 s 2500 v triggering parameter symbol test conditions values units maximum peak gate power p gm 8 w maximum average gate power p g(av) 2 maximum peak gate current i gm 2a maximum peak negati ve gate voltage -v gm 10 v maximum gate voltage required to trigger v gt t j = - 40 c anode supply = ? 6 v resistive load 3 v t j = 25 c 2 t j = 125 c 1 maximum gate current required to trigger i gt t j = - 40 c 90 ma t j = 25 c 60 t j = 125 c 35 maximum gate voltage th at will not trigger v gd t j = 125 c, rated v drm applied 0.2 v maximum gate current th at will not trigger i gd 2ma
vs-p100 series www.vishay.com vishay semiconductors revision: 27-mar-14 3 document number: 93754 for technical questions within your region: diodesamericas@vishay.com , diodesasia@vishay.com , diodeseurope@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 note (1) a mounting compound is reco mmended and the torque should be checked after a period of 3 hours to allow for the spread of the co mpound fig. 1 - current ratings nomogram (1 module per heatsink) fig. 2 - on-state power loss characteristics fig. 3 - on-state power loss characteristics thermal and mechanical specifications parameter symbol test conditions values units maximum junction operating ? and storage temperature range t j , t stg -40 to 125 c maximum thermal resistance, ? junction to case per junction r thjc dc operation 2.24 k/w maximum thermal resistance, ? case to heatsink r thcs mounting surface, smooth and greased 0.10 mounting torque, base to heatsink (1) 4nm approximate weight 58 g 2.0 oz. case style pace-pak (d-19) maximum total power loss (w) total output current (a) 5101520 25 0 0 60 50 40 30 20 10 93754_01a ~ + - 180 ( s ine) t j = 125 c maximum total power loss (w) maximum allowa b le am b ient temperature (c) 25 75 50 100 125 0 60 50 40 30 20 10 0 93754_01b r th s a = 15 k/w - r 2 k/w 3 k/w 7 k/w 10 k/w 5 k/w maximum average on- s tate power loss (w) average on- s tate current (a) 10 15 05 15 10 5 0 93754_02 180 120 90 60 30 rm s limit ? conduction angle t j = 125 c per junction maximum average on- s tate power loss (w) average on- s tate current (a) 20 01015 5 20 10 15 5 0 93754_03 dc 180 120 90 60 30 rm s limit t j = 125 c per junction conduction period ?
vs-p100 series www.vishay.com vishay semiconductors revision: 27-mar-14 4 document number: 93754 for technical questions within your region: diodesamericas@vishay.com , diodesasia@vishay.com , diodeseurope@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 fig. 4 - current ra tings characteristics fig. 5 - on-state volt age drop characteristics fig. 6 - maximum non-re petitive surge current fig. 7 - maximum non-re petitive surge current fig. 8 - thermal impedance z thjc characteristics maximum allowa b le case temperature (c) total output current (a) 10 20 51525 30 0 70 80 90 100 110 120 130 93754_04 180 ( s ine) 180 (rect.) fully turned-on per module instantaneous on- s tate current (a) instantaneous on- s tate voltage (v) 0123456 1 100 10 1000 93754_05 t j = 25 c t j = 125 c per junction peak half s ine wave on- s tate current (a) num b er of equal amplitu d e half cycle current pulses (n) 10 100 1 150 200 300 250 350 93754_06 per junction at any rated load condition and with rated v rrm applied following s urge. initial t j = 125 c at 60 hz 0.0083 s at 50 hz 0.0100 s peak half s ine wave on- s tate current (a) pulse train duration (s) 0.1 1 0.01 100 150 200 250 300 350 400 93754_07 maximum non-repetitive s urge current ver s u s pul s e train duration. control of conduction may not be maintained. initial t j = 125 c no voltage reapplied rated v rrm reapplied per junction 0.01 0.1 1 10 0.0001 0.001 0.01 0.1 10 1 s quare wave pulse duration (s) z thjc - transient thermal impe d ance (k/w) 93754_08 per junction s teady s tate value r thjc = 2.24 k/w (dc operation)
vs-p100 series www.vishay.com vishay semiconductors revision: 27-mar-14 5 document number: 93754 for technical questions within your region: diodesamericas@vishay.com , diodesasia@vishay.com , diodeseurope@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 fig. 9 - gate characteristics ordering information table 0.1 1 10 100 0.001 93754_09 instantaneous g ate current (a) instantaneous g ate voltage (v) 0.01 0.1 1 10 100 (1) (2) (3) (4) (1) p g m = 10 w, t p = 5 m s (2) p g m = 20 w, t p = 25 m s (3) p g m = 50 w, t p = 1 m s (4) p g m = 100 w, t p = 500 s fre q uency limited by p g (av) (b) (a) t j = 25 c t j = 125 c t j = 40 c v g d i g d rectangular gate pul s e (a) recommended load line for rated di/dt: 10 v, 20 , t r 1 s (b) recommended load line for rated di/dt: 10 v, 65 , t r 1 s 1 - vishay semiconductors product 2 - module type 6 - k = optional voltage suppression 7 - w = optional freewheeling diode 4 - circuit configuration - voltage code 1 = 400 v 2 = 600 v 3 = 800 v 4 = 1000 v 5 = 1200 v 5 - current rating 1 = 25 a dc (p100 series) 4 = 40 a dc (p400 series) 0 = single phase, hybrid bridge common cathode 2 = single phase, hybrid bridge doubler connection 3 = single phase, all scr bridge 3 device code 1 3 2 4 5 6 7 vs- 1 p02kw
vs-p100 series www.vishay.com vishay semiconductors revision: 27-mar-14 6 document number: 93754 for technical questions within your region: diodesamericas@vishay.com , diodesasia@vishay.com , diodeseurope@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 note (1) to complete code refer to voltage ratings ta ble, i.e.: for 600 v p10. w complete code is p102w circuit configuration circuit description circuit configuration code schematic diagram terminal positions single phase, hybrid bridge common cathode 0 single phase, hybrid bridge doubler connection 2 single phase, all scr bridge 3 coding (1) circuit description circuit configuration code basic series with voltage suppression with freewheeling diode with both voltage suppression and freewheeling diode single phase, hybrid bridge common cathode 0 p10. p10.k p10.w p10.kw single phase, hybrid bridge doubler connection 2 p12. p12.k -- single phase, all scr bridge 3 p13. p13.k -- links to related documents dimensions www.vishay.com/doc?95335 g 1 ac2 ac1 g 2 (-) (+) ac1 g 1- ac2 g 2+ g 2 g 1 ac1 ac2 (-) (+) ac1 g 1- ac2 g 2+ g 1 g 3 ac2 ac1 (-) (+) g 2 g 4 ac2 g 2- ac1 g 3 g 1 g 4 +
document number: 95335 for tec hnical questions, contact: indmodules@vishay.com www.vishay.com revision: 24-jul-08 1 d-19 pace-pak outline dimensions vishay semiconductors dimensions in millimeters (inches) 0.9 x 45 (0.035 x 45) 12.7 (0.50) 63.5 (2.50) 45 (1.77) 12.7 (0.50) ? 1.65 (0.06) fast-on 6.35 x 0.8 (0.25 x 0.03) 4.6 (0.18) 2.5 (0.10) max. 5.2 (0.20) 48.7 (1.91) 33.8 (1.33) 32.5 (1.28) max. 23.2 (0.91) 15.5 (0.61) max. 25 (0.98) max.
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